我今天嘗試將elevator.v 讀進去以後synthesis
再將它用write des 寫成elevator2.v檔
但是我再將elevator2.v檔讀進來時 出現以下錯誤:
Error : The sub-module "DVL_BUF" is not defined in the module "elevator"
整個過程如下:
[ckmarkoh@hebe ~/SOCV/pa1 ]$ ./logicSim.ref-32
QuteRTL> rea de ./elevator_design/elevator.v
> Parsing Verilog File : /home/ckmarkoh/SOCV/pa1/elevator_design/elevator.v
...
==================================================
==> Total 1 Module(s)
==> Top Module : elevator
DESIGN @ elevator> syn
=== Start Synthesis ...
> Synthesizing Module : elevator ...
=== Cell Collection and Naming ...
=== Set CktModule ...
==================================================
==> Total 1 Module(s)
==> Top Module : elevator
DESIGN @ elevator> write des elevator2.v
Write design start...
Write design successfully!!
DESIGN @ elevator>
DESIGN @ elevator> q -f
[ckmarkoh@hebe ~/SOCV/pa1 ]$ ./logicSim.ref-32
QuteRTL> rea des elevator2.v
> Parsing Verilog File : /home/ckmarkoh/SOCV/pa1/elevator2.v ...
==================================================
==> Total 1 Module(s)
==> Top Module : elevator
Error : The sub-module "DVL_BUF" is not defined in the module "elevator"
[ckmarkoh@hebe ~/SOCV/pa1 ]$
請問為何會發生這種Error?