※ [本文轉錄自 Electronics 看板 #1RAw_JSS ]
作者: suspect1 () 看板: Electronics
標題: [問題] SR latch
時間: Thu Jun 21 22:01:53 2018
板上的大大可以解釋一下這個考題的意思嗎？
a SR latch implemented with 2 Nand gates
(1)changes in 2 outputs always take place with time difference of a gate
delay ? (True or False)
(2)It takes shorter time to set Q to 1 than reset Q to 0 (True or False)