今天唸到這個問題
三年前有人在板上問過了
但是我看了還是搞不太懂
請各位幫忙指點一下各個選項要表達的意思
如果有張凡課本可直接參考上冊P437.P438的練習題
題目:A group of students have been debating the efficiency of five-stage pipel ine when one student pointed out that not all instructions are active in every stage of the pipeline.After deciding to ignore the effects of hazards,they ma de the following five statements.Which ones are correct?
1.Allowing jumps,branches,and ALU instructions to take fewer stages than the f ive required by the load instruction will increase pipeline performance under all circumstances.
2.Trying to allow some instructions to take fewer cycles does ont help,since t he throughput is determined by the clock cycle;the number of pipe stages per i nstruction affects latency,not throughput.
3.Allowing jumps,branches,and ALU operations to take fewer cycles only helps w hen no loads or stores are in the pipeline,so the benefits are small.
4.You cannot make ALU instructions take fewer cycles because of the write-back of the result,but there is some opportunity for improvement.
5.Instead of trying to make instructions take fewer cycles,we should explore m aking the pipeline longer,so that instructions take more cycles,but the cycles are shorter.This could improve performance.
ANS:2 and 5 are correct

2. throughput 被 cycle time 決定呀5. 管線越多級，"理論"上時間就會減少好幾倍

1. load 仍要五個cycle所以並不會變 而要取最多cycle數所以performance不變 2. 總時間為（IC - 1 + stage數）*cycle time 一般IC極大於stage數所以忽略stage 所以總體效能（throughput)會取決於cycle time 降低stage數只會影響單一instruction的latency 3. ALU沒辦法減少cycle 因為他一定要write back(完整五個stage) 4. 前面是對的 正是因為沒辦法減少 所以仍會取最長的5個stage (我是覺得有點爭議啦...硬要說的話 把cycle time 減少 performance不就變好了...）5. cycle變多所以cycle time變短 所以performance提升補充一下5 原先5個stage的時間拆成更多stage 所以一個stage(cycle time) 時間變短

我瞭解了謝謝樓上兩位大大！