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<月薪20萬起～美商Cisco思科台灣全職 (Full Time) 職缺>ASIC 技術主管
～月薪新台幣20萬元起~
申請截止日：2018年9月30日
此次主要招募對像為ASIC 技術主管, 請投遞中英文履歷至
Cisco思科人力資源大中華區聯絡人
Sarah Shen| [email protected] | +86 21 2407 3253
工作地點：台北市11052信義路四段460號12樓
<薪資福利>
薪資: 月薪新台幣20萬元起~12個月
獎金：視個人績效與公司營運
特休假：一年12天（帶薪病假24天另計）, 生日假1天，公益假5天，緊急事假4週
加班費制度：比照勞基法
<工作型態>
上班時間：週休二日，彈性工作制
管理責任：負擔技術管理責任
最低資格:
*需要3年以上ASIC 硬體設計經驗，熟悉Verilog RTL 語言
*熟悉IC 設計流程，從功能規格，實現，驗証到量產
*英文聽、說流利。
*有以太網路經驗和TCP/IP 經驗佳
*有驗證System verilog 或 UVM 經驗佳，但非必須
*電機或資訊碩士
What You'll Do
The INSBU nexus 9k group is looking for an experienced Technical Leader to drive existing projects and engage in new development of our Nexus 9K family. The ideal candidate will have an ASIC design ba
It used to be that high-speed packet forwarding was performed in dedicated ASIC designs. These days we are looking to make those ASICs more general and programmable. P4 has been proposed as a domain-s
It used to be that high-speed packet forwarding was performed in dedicated ASIC designs. These days we are looking to make those ASICs more general and programmable. P4 has been proposed as a domain-s
Who You'll Work With
Who You'll Work With
INSBU developed the Nexus 9000 line of data center switches and Application Centric Infrastructure, Cisco’s premier datacenter SDN solution. Our team within INSBU is responsible for driving integrati
INSBU developed the Nexus 9000 line of data center switches and Application Centric Infrastructure, Cisco’s premier datacenter SDN solution. Our team within INSBU is responsible for driving integrati
INSBU develops high-performance switches for the data center and for the cloud. You will be working with the team that develops the ASICs at the heart of each of these switch products. There are only
INSBU develops high-performance switches for the data center and for the cloud. You will be working with the team that develops the ASICs at the heart of each of these switch products. There are only
Who You Are
Cisco INSBU is looking for a passionate ASIC Designer to join our R&D team. This role involves working on cutting-edge high performance ASIC design from specification to RTL implementation. The new me
hardware and network OS developers.
· Develop network processing ASIC architecture and micro architecture specification
· Design high performance and high quality ASIC design from specification to RTL implementation
· Perform ASIC verification, synthesis, timing analysis IP integration
· Participating system/board level bring up, debugging and support
Experience Required
· 3 years or more networking ASIC experience
· Strong tracking record of ASIC design from concept to mass production
· Hands-on experience on Verilog HDL coding and verification
· Experience of high performance ASIC design from specification to system bringing up
· Ethernet and TCP/IP networking concept and protocols knowledge
· Knowledge of System Verilog and UVM verification methodology
· Highly motivated, positive, detail oriented and responsible
· Highly motivated, positive, detail oriented and responsible
· Good team player and good communication skills
· MSEE/MSCS
· MSEE/MSCS