公司名稱: Apple Japan
目前日本蘋果還有需要一些硬體的人才，工作地點皆為東京。有興趣可以私訊問我。要準
備英文履歷喔。
1. Modeling and Verification Engineer, Digital Mixed-Signal.
https://reurl.cc/Y1VWz4
Key Qualificiatins.
a. 5+ years of experience in developing and verifying real-numbered analog
behavioral models in Systemverilog.
b. Solid understanding of Systemverilog, RNM, UDN/UDT/UDR, wreal, Verilog-AMS.
c. Experience in Systemverilog testbench development.
d. Understanding of analog/mixed-signal blocks like Filter, opAmp, ADC, DAC,
VCO, A/DPLL, Serdes, etc.
e. Working experience in Cadence Virtuoso Schematic Composer and ADE.
f. Very good understanding of analog, and design background (to analyze
verification results) is a strong plus.
g. Experience in writing scripts in languages such as Perl or Python.
h. Business-level at English communication in both speaking and writing.
i. Team spirit, excellent communication skills and the desire to take on
diverse challenges.