[求救] 積電作業 HW3 verilog

作者: TommyKSHS (湯米)   2011-12-13 22:52:09
我跑了 ncverilog +access+r tb_Comparator_51.v lib.v Comparator_51.v
這個指令後
出現了
The tool has encountered an unexpected condition and must exit.
Contact Cadence Design Systems customer support about this
problem and provide enough information to help us reproduce it,
including the logfile that contains this error message.
TOOL: ncsim 08.20-s024
HOSTNAME: cad32
OPERATING SYSTEM: SunOS 5.10 Generic_118833-24 sun4u
MESSAGE: sv_seghandler - SIGSEGV while handling SIGSEGV
System task: $fsdbDumpvars
file: ./tb_Comparator_51.v
line: 52
有哪位先進知道這該怎辦…
原本以為逃離資結就不會有 segmentation fault 了
結果連 verilog 都會 segmentation fault 是怎樣… QQQQ

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