課程名稱︰數位電子與數位電路
課程性質︰選修
課程教師：歐陽明
開課學院：電資學院
開課系所︰資工系
考試日期（年月日）︰2013.01.07
考試時限（分鐘）：
試題 :
Final Exam of Circuits and Electronics 2013/1/7
For this exam, if not specified, use the following parameters.
Use K'_n = 100 μA/V^2, K'_p = 40 μA/V^2, V_TN = 0.6 V, and V_TP = -0.6 V
unless otherwise indicated.
(1) (5%) Please explain how to read the content from the 1-T dynamic memory
cell below.
http://i.imgur.com/pqMDxBu.png
(2) (5%) Please explain how to write a bit "1" into the content of a 6-T static
memory cell below.
http://i.imgur.com/qoJVxOB.png
(3) (5%) Please explain the function/operation of a Flash memory cell below.
http://i.imgur.com/qEY4wOM.png
(4) (10%) What are the contents of the ROM below. (All FETs are NMOS).
http://i.imgur.com/Y1vYiE8.png
(5) (5%) What are the logic functions for Q with input 1 and 2 in the
flip-flop below?
http://i.imgur.com/rFbVOzX.png
(6) (10%) A sequential circuit with two D flip-flops A and B, one input X, and
one output Z.
(a) Please write the logic equations for the input of two D flip-flops,
and output Z.
(b) Given input sequence X = 0, 1, 0, 1, 0, 0, 1, 1, 0, 1, what will be
the output Z for these input?
http://i.imgur.com/o4K2h8Z.png
(7) (10%) A sequential circuit with one D flip-flop A, two input X, Y, and one
output Z.
(a) Please write the logic equations for the input of one D flip-flops and
output Z.
(b) Given input sequence (X,Y) as (1,1), (1,0), (0,1), (0,0), (1,0),
(0,1), (0,0), what will be the output Z for these input?
http://i.imgur.com/iOpcVka.png
(8) (10%) Design a resistive load inverter to operate from a 2.0 V power supply
with a power dissipation of 50 micro W. (micro: 10^(-6)).
(9) (5%) Make a truth table and write an expression for the logic function
below.
http://i.imgur.com/rtJUW6m.png
(10) (20%) For the CMOS inverter below, when given the input below, what will
be the output (rising voltage)? Please give the output equation and
roughly draw the curve.
http://i.imgur.com/zmapcYQ.png
(11) (15%)
(a) What is the logic function that is implemented by the gate below?
(c) What are the W/L ratios for the FETs, based on the reference inverter
design of Fig. 10.
http://i.imgur.com/smY2DbJ.png
http://i.imgur.com/guYwYVa.png (Fig. 10 Reference design)