Hi Phil
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I am sorry.
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The value 0008h or 0h of CPU MSR 0x19a is disabled, and the value 10h of CPU MSR 0x19a is enabled.
It means that the results of experiments on December, 1 are under disabled mode, not enabled mode.
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So we redo the test, the result is below,
CPU MSR 0x19a set to enabled under DOS, SMI test still fails under DOS.
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And we check the value of CPU MSR 0x19a when demo BIOS CPU ALP-BIOS-SCU-038-REL.bin is flashed, the result is below,
The value of CPU MSR 0x19a is 0002 under DOS when demo BIOS CPU ALP-BIOS-SCU-038-REL.bin is flashed.
The value of CPU MSR 0x19a is 0000 under Windows when demo BIOS CPU ALP-BIOS-SCU-038-REL.bin is flashed.
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Thanks
Kant
ꀠ_____ ꀊ
From: Kant Shih
Sent: Thursday, December 01, 2011 5:49 PM
To: Phil Xing
Subject: RE: HSD Client-CE s3624998 - [SMI triggered delay makes CPU saved/restore data incorrect] [New Sighting]
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Internal only
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Dear Phil.
?????fail, ?????????. The result is positive.
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????:
1.ꂠꂠꂠ DOS ??debug32 ??CPU MSR 0x19a ??, ???0008h, ????debug32 ??0??CPU MSR 0x19a, ?????????????????0
2.ꂠꂠꂠ DOS ???IRU, ??Tools/SMI Latency, ??????, ???????
?????, CPU MSR 0x19a ?????0008h
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3.
DOS ??debug32??CPU MSR 0x19a ?????
mov ecx, 19a
rdmsr
?????eax
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4.
DOS ??debug32??0??CPU MSR 0x19a ???
mov ecx, 19a
mov 汢dx, 0
mov 汢ax, 0
wrmsr
????????edx : eax
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Thanks
Kant
ꀠ_____ ꀊ
From: Phil Xing
Sent: Thursday, December 01, 2011 4:22 PM
To: Tie, Shuangen; Den Wu
Cc: Boudrez, Wouter; Liao, Clark
Subject: RE: HSD Client-CE s3624998 - [SMI triggered delay makes CPU saved/restore data incorrect] [New Sighting]
ꀊ
Hi Michael,
ꂠꂠꂠꀠThanks for the information, we will try it and keep you posted.
ꀊ
B.R.
Phil @8888
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From: Tie, Shuangen [m
Sent: Thursday, December 01, 2011 4:14 PM
To: Phil Xing; Den Wu
Cc: Boudrez, Wouter; Liao, Clark
Subject: FW: HSD Client-CE s3624998 - [SMI triggered delay makes CPU saved/restore data incorrect] [New Sighting]
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Hi Phil,
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Please try to disable the clock modulation (MSR 0x19a) on your platform to see if the issue goes away. If that doesn急 help, please provide your test case, environment, details on issue reproduction etc so that we could reproduce it here in our lab.
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And, please also provide your feedback through VIP. Thanks!
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Regards/Michael
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???: Den Wu [mail
????: 2011?11?29? ?? 08:47
???: He. Bluesky (CIC); Shoddy Lin
??: Yang. Roy (CIC); Meggie Leu; Bini Yi; [email protected]; Wu. Kimi (TPE); Owen Lu; Zhang. Jonson (CIC)
??: RE: [Compal / QEX00 ]: SMI Event missing
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Dear Bluesky,
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Sorry for late, about OAK trail SMI fail issue, we挙e feedback to Intel and key in sighting report.
The Sighting number is AS-1111-02D0
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Root cause:ꀠOnce our program call SMI, CPU should trigger immediately.
But it has fail rate that CPU not terminated background command/program and active SMI at once.
SMI trigger was delayed after the background program has done, so the feedback status is changed and unpredictable.
(Detail as below mail)
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Verify detail:
1)ꂠꂠꀠThe original RIP address is 0x7effba87, which address is our program before call SMI.
2)ꂠꂠꀠIn the failed pass, CPU did not enter SMM immediately and continue execute followed instruction to 0x7f13A659.
Description: ??: cid:[email protected]
In this case, CPU register is changed by above instruction and saved wrong state to SMRAM.
When SMI callback function needs to be execute by those CPU register and return value to caller, the unpredictable error will occurred.
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Overall, due to BIOS could Not know when the delay SMI will be triggered, the SMI delay is unpredictable
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B.R.
Den
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ꀊ
Regards,
ꀊ
Wouter Boudrez
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